Multiple Exposure Patterning in a Single Photoresist Layer

VT researchers have developed a photolithography technique that cuts the cost of double patterning in half, simplifies single exposure photolithography, and significantly reduces diffraction distortion of complex patterns. This approach also supports higher processing throughput and greater fidelity of the smallest features. The result is the potential for the semiconductor industry to extend the life of conventional photolithography equipment through several additional generations of semiconductor feature reduction.


By coupling multiple exposures with image reversal, this technology reduces photolithography processing steps up to half. Additionally, this methodology can also reduce the effect of diffraction distortions of other photolithographic techniques. Optimized decomposition of mask design into separate masks for each exposure is also incorporated into this invention – enabling implementation within electronic design automation tools.


Also disclosed is a novel photolithography apparatus and methodology for achieving soft or hard photoresist baking steps within photolithography equipment. By incorporating baking steps within the photolithography equipment, mask alignment requirements are improved and processing time can be saved compared to removing a wafer from the equipment for baking. For photolithography using image reversal photoresist, such in-situ baking provides additional process time and throughput advantages between exposures.

Patent Information:
For Information, Contact:
Grant Brewer
Senior Licensing Associate
Virginia Tech Intellectual Properties, Inc.
(540) 231-6648
Coumba Ndoye
Marius Orlowski