Islanding Detection Using Phase-Locked-Loop Small-Signal Instability For Three-Phase Power Inverters

Description:
A simple and effective anti-islanding detection is required to meet IEEE standard 1547 for every distributed generation unit. Many research papers and patents work on this issue, and there exists lots of solutions. All the existing solutions suffer the complicated design and lots of implementation procesess. Some of them tend to destabilize the grid or violate the other standards, such as low-voltage ride-through (LVRT) requirements. Two anti-islanding detection algorithms in three-phase distributed generation unit are proposed in this patent application. Both methods utilize the phase-locked-loop system with a slight modification. Both methods will destabilize the PLL output and trip the detection signal. Compared to others, the proposed solutions feature a simple implementation, clear modeling tool for tuning parameters, and won't violate the LVRT requirement.
Patent Information:
Category(s):
Electrical
For Information, Contact:
Li Chen
Licensing Associate
Virginia Tech Intellectual Properties, Inc.
(540) 443-9217
lchen@vtip.org
Inventors:
Dong Dong
Dushan Boroyevich
Paolo Mattavelli
Bo Wen
Keywords:
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