Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses

A method of providing permanent very low resistance connections between two metal (e.g. Cu and Ti lines) intersecting lines separated by a thin dielectric has been demonstrated. In order to create such a permanent connection, one metal line may be grounded, and a linear voltage ramp, or a voltage pulse, is applied to the other metal line. Under electric stress a Cu filament is formed between Cu and Ti lines. For this method to work, the metal lines and the intermediate dielectric are required to have certain properties. One metal line must consist of an "active" metal, i.e. such metal that can undergo an oxidation reaction, Cu->Cu+e-, in the dielectric between the lines. Moreover, the metal ions are required to have sufficiently high mobility in the dielectric. A few good choices for an active metal are: Cu, Ag, and Ni, with Cu as the most suitable choice, as it is relatively cheap, it is a very good electric conductor, and it is already being used in CMOS backend interconnect system. The counter electrode cannot be a perfectly inert metal. An inert metal, such as platinum, would stop Cu ion diffusion into the counterelectrode. For our method to work, we need a metal which has a low stopping power for active metal ion diffusion. A good choice for such an electrode would be Ti. Our method would not work as SiCOH:H, the formation of final low resistance via is a two level process. One would apply a first voltage ramp and would observe, at a low voltage value of typically 1V, a resistance transition, typically from 200 MOhm to ca 120kOhm. Upon the application of second voltage ramp, or another voltage pulse, one would observe, at a voltage value of typically 1V, a transition from 120kOhm to 1-10 Ohm, depending on the limiting (so called compliance) current. The method has been demonstrated (reduced to praxis) on samples manufactured by Intel and sent to VTech for characterization under the SRC project listed above. The specific characterization has been done in Whitemore 617 characterization lab. The method of creating permanent vias has been conceived at Virginia Tech.
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For Information, Contact:
Grant Brewer
Senior Licensing Associate
Virginia Tech Intellectual Properties, Inc.
(540) 231-6648
Marius Orlowski
Gargi Ghosh
Anshuman Verma